Master serial interface compatible with the popular SPI standard.
Features a simple command interface and permits multiple SPI slaves to be controlled directly from your FPGA, CPLD or ASIC device.
SPI Master Serial Interface Controller
Overview
Key Features
- SPI compliant
- Full-duplex or half-duplex operation
- Simple command interface
- Input and output FIFOs
- Supports up the 16 slave devices
- Configurable clock polarity (CPOL)
- Configurable clock phase (CPHA)
- Configurable clock frequency
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All
Availability
Immediate
Related IPs
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- APB SPI (Serial Peripheral Interface) master and slave
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa
- A bridge to convert the slave SPI interface to the master UART interface and vice versa
- Standard SPI Single Master
- Serial Peripheral Interconnect Master & Slave Interface Controller