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subLVDS IP

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Compare 32 subLVDS IP from 5 vendors (1 - 10)
  • Library of LVDS IOs cells for TSMC 65LP
    • TSMC 65 LP
    • 2.5V/1.2V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 65LP
  • Library of LVDS IOs cells for TSMC 40LP
    • TSMC 40 LP
    • 2.5V/1.1V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 40LP
  • subLVDS I/O Pad Set
    • Input receive sensitivity of 50mV peak differential (without hysteresis)
    • Common mode range from 0.4V to 1.6V (limited by Power Supply)
    • Powered by 1.8V I/O and 1.1V core supplies
    • Power consumption: 3.4 mW max @ 800 MHz
  • subLVDS IO Pad Set
    • Input receive sensitivity of 50mV peak differential (without hysteresis)
    • Common mode range from 0.4V to 1.8V (limited by power supply)
    • Powered by 1.8V I/O and 1.1V core supplies
    • Power consumption: 4.94 mW max @ 600 MHz
  • subLVDS IO Pad Set
    • Powered from 1.8V ±10% and 1.0V(±10%) to 1.1V(-10%/+5%) core power supplies
    • Operates up to 1GHz (2Gbps)
    • Input receive sensitivity of 50mV peak differential (without hysteresis)
    • Common mode range from 0.4V to 1.4V (limited by Power Supply)
  • Camera SLVS-EC/sub-LVDS/CMOS1.8 combo Receiver 2.4G/800Mbps/166MHz 8-Lane
    • SLVS-EC ver.1.2 compliant
    • Supporting for four kind Differential Input Signals
    • Xtal Input Clock Frequency Selectable 24MHz / 37.125MHz / 54MHz / 72MHz
    • Maximum Input Clock Frequency ~400MHz (sub-LVDS)
  • Camera MIPI D-PHY v1-1 1.5Gbps / sub-LVDS combo Receiver 4-Lane
    • MIPI D-PHY v1-1 / MIPI CSI2 compliant
    • Supporting for four kind Differential Input Signals:
    • Maximum Input Clock Frequency: ~750MHz
    • Maximum Input Data Transfer Rate: ~1.5Gbps
  • MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane
    • MIPI DPHY v1-1 / MIPI CSI2 compliant
    • Differential signal of almost CIS serial outputs support
    • Input Clock Frequency:
    • (sub-LVDS mode Clock Generator Input) SCK=~1000MHz
  • GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v SUBLVDSTX
    • Process: GF 28nm SLP 1.0V/1.8V CMOS process
    • Supply voltage: 1.62V<=AV18_TX(AVDD)<=1.98V,0.9V<=AVDD2(DV10)<=1.1
    • Mos device type: egpfet, egnfet, pfet, nfet
    • Operating junction temperature: - 40°C ~ +25°C ~ +125°C
  • SMIC 55nm sub-LVDS Receiver
    • Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
    • 10 data channels / 2 clock channel integrated
    • Maximum serial data rate per channel: 1Gbps
    • Supports up to 20-bit CMOS parallel input (DVP input mode)
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