The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word. The receiver defined in this IP is only required to interface with the image sensor. The receiver consists of two LVDS receiver cells (Strobe and Data) followed by a 1:4 de-serializer. Only Data-Strobe mode needs to be supported in this design. Therefore the clock may always be recovered using a DDR Flop clocked by the XOR of Strobe and Data. In addition, only Sub-LVDS electrical requirements must be met.
Sub-LVDS receiver followed by 1:4 de-serializer
Overview
Key Features
- Sub-low voltage differential signaling input: VID = 25mV MIN.
- Converts the subLVDS strobe/data (up to 960 Mbps throughput bandwidth) back into parallel 4 bits of CMOS data/strobe
- Power-down control function
- Full industrial operating temperature range -40 ~ +125 °C
- SMIC 0.13um Logic Salicide Process (1p6m, 1.2V/2.5V)
- On chip 100ohm resistance between receivers’ each positive input and negative input
- Positive clock edge with data output
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- 32:1 serializer followed by sub-LVDS drivers
- DisplayPort 1.4 FEC Receiver (Rx)
- SMIC 55nm sub-LVDS Receiver
- SMIC 55nm sub-LVDS Receiver
- HDMI 1.4/2.0/2.1 receiver IP
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP