CodaCache® Last Level Cache IP

Overview

Key Features

• Standalone IP
• 1.2 GHz frequency in 16FF+TT process
• Protocol interoperability: AMBA AXI 4
• 64 Byte cache line size
• Cache size up to 8MB per AXI port
• Scratchpad RAM configurations
• Configurable way associativity from 1 to 16
• Way partitioning
• Cache flushing
• ECC protection
• Helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults

Benefits

• LLC Implementation: Provides a dedicated and configurable last-level cache that is significant and high-capacity for the SoC. The LLC acts as a buffer between the main memory and the processor cores, improving data access latency and reducing memory bandwidth requirements.
• Scalability and Configurability: Highly scalable and configurable, accommodating various SoC designs. It supports different cache sizes, associativity levels, and coherence granularities, allowing designers to tailor the cache hierarchy to their specific requirements. This flexibility ensures efficient utilization of available resources and enables scalability for diverse application scenarios.
• Power Management: Incorporates power management techniques to optimize energy consumption in SoC designs. These power management techniques help reduce power consumption and extend battery life in mobile devices.
• Performance Optimization: Enhances system performance through efficient cache access and reduced memory access latency. It minimizes cache misses by providing a sizeable last-level cache closer to the processor cores, enabling faster data access, and reducing the need for frequent memory accesses. This improves overall system performance and responsiveness.
• Reliability and Error Detection: Includes error detection mechanisms to ensure data integrity and reliability. It incorporates error correction codes (ECC) and parity checking to detect and correct errors in cache data. These error detection capabilities enhance system robustness and reduce the risk of data corruption.
• Ecosystem Compatibility: Seamlessly integrates with the broader design ecosystem, supporting industry-standard interfaces and third-party IP blocks. It ensures compatibility with various processor cores, interconnect fabrics, and verification environments, enabling designers to leverage existing IP resources and design flows, streamlining the integration process.

Block Diagram

Applications

• Automotive, Mobility, Wireless, Consumer Electronics, IoT, Server, Networking, and Industrial SoCs that require low-latency and high bandwidth Cache Coherency.

Technical Specifications