This is a collection FIFO and Elastic Buffers.
This carry following kind of FIFO and Elastic Buffers -
1. First In First Out (FIFO) (Sync/Async) with internal Registers.
2. First In First Out (FIFO) (Sync/Async) with OnChip Dual Port SRAM.
3. First In First Out (FIFO) (Sync) with OnChip single Port SRAM.
4. Elastic Buffer
This is a Collection of different kind of FIFOs and Elastic buffers.
Overview
Key Features
- Features -
- This is a Generic fifo with configurable Depth, Configurable Width and Clock Domain Crossing options.
- Fully Stable, CDC Proven, Non2**n depth supported FIFOs.
Benefits
- 1. Using Stable and Tested Standard block decrease time to clean up issues in later stages.
- 3. Makes IP More stable to operate.
Applications
- Internal IP Component Block
- can be used inside any IP/SOC.
Deliverables
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
Technical Specifications
Maturity
High, Stable, Tested
Availability
Avaliable
Related IPs
- This is collection of Synchronization Components can be used to synchronize across different clock domains for control and Data Transfer
- Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.
- ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads
- Software solution targeting the configuration of Ethernet switches and endpoints in TSN networks