IP Catalog > Memory & Libraries IP > Embedded Memories IP > FIFO/LIFO IP > This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.

This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.

Overview

This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Memory is implemented by Registers.
It has option to select CDC mythology and CDC Clock ratio to make it more stable operating at different set of freq.

Key Features

  • 1. Configurable Depth.
  • 2. Configurable Width.
  • 3. Configurable Clock freq.

Benefits

  • 1. Fully stable operation.
  • 2. Non-2**n depth supported.
  • 3. Dip-In and Data Available support.
  • 4. CDC method and CDC clock ratio selectable

Applications

  • Internal IP Component Block
  • can be used inside any IP/SOC.

Deliverables

  • Standard Deliverables list -
  • 1. Source Code in verilog.
  • 2. Test Bench.
  • 3. Simulation Scripts.
  • 4. Synthesys scripts.
  • 5. Documentation
  • 6. User Guide.

Technical Specifications

Maturity
Final, Stable, Tested
Availability
Avaliable
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