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Compare 137 Other from 28 vendors (1 - 10)
  • xSPI NOR Flash controller
    • Memory mapped access to the connected flash devices
    • Continuous Burst transfer support
    • Auto boot support
    Block Diagram -- xSPI NOR Flash controller
  • Hyperbus Flash Memory Controller
    • Compatible with spansion hyperbus based memory products.
    • 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.
    Block Diagram -- Hyperbus Flash Memory Controller
  • Quad-SPI FLASH Controller AHB
    • AHB Memory Mapped Access
    • Auto-Copy DMA Boot Support
    • DMA controller
    Block Diagram -- Quad-SPI FLASH Controller AHB
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • Simulation VIP for Toggle NAND
    • Speed
    • Up to 200MHz or 400Mbps per DQ pin
    • Up to 600MHz or 1200Mbps per DQ pin (Version 3.0/4.0)
    • Bits per Cell
    Block Diagram -- Simulation VIP for Toggle NAND
  • Simulation VIP for SPI NAND
    • Operation Modes
    • Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) and serial mode 0 and mode 3
    • Pins
    • HOLD# and WP# Pins functionalities
    Block Diagram -- Simulation VIP for SPI NAND
  • Direct Memory Access Controller
    • 32-bit or 8-bit internal registers access
    • 32-bit transmission address range
    • Transaction size from 1B up to 16MB
    • Four transmission channels
    Block Diagram -- Direct Memory Access Controller
  • DO-254 SDRAM Controller
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Compliant to JEDEC Standard No. 21-C Page 3.11.5.1 Release 12
    • Single clock domain fully synchronous design
    • Configurable to support any SDRAM device
    Block Diagram -- DO-254 SDRAM Controller
  • SD 5.1 / eMMC 5.1 Host Controller IP
    • SD IP Features :
    • Support SD system specification version 5.1
    • Support Application Performance Class 1.
    • Backward compatible to SD2.0 host
    Block Diagram -- SD 5.1 / eMMC 5.1 Host Controller IP
  • AHB Parallel Flash Controller
    • Interfaces AHB bus to Parallel SuperFlash device(s)
    • AMBA® AHB Compatible
    • Supports 8-bit, 16-bit and 32-bit external modes
    • Supports word (32-bit) AHB accesses to all configurations
    Block Diagram -- AHB Parallel Flash Controller
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Semiconductor IP