PCI Express IP

The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.

The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.

The AXI Bridge for PCIe IP core is the IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.
The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

Implements PCIe 6.0 Specification at 64 GT/s
Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
Designed for easy integration with Alphawave PipeCORE™ PCIe PHY IP
Key IP features configurable to optimize IP for exact application requirements

The PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s).
It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.

The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0.
The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics.

The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.

The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.

Supports 2.5Gb/s serial data rate
Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
Data and clock recovery from serial stream on the PCI Express bus

Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0
This Avalon® Streaming Interface Hard IP supports PCIe 1.0, 2.0, and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SR-IOV functionality.