PCI Express Phy IP

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Compare 297 PCI Express Phy IP from 24 vendors (1 - 10)
  • PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
    • The PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s).
    • It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.
    Block Diagram -- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
  • PCI Express PIPE PHY Transceiver
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PIPE PHY Transceiver
  • PCIe Gen 6 Phy
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • PCIe Gen 6 Phy IPPCIe Gen 6 Phy IPComprehensive real-time diagnostic, monitor, and test features
    Block Diagram -- PCIe Gen 6 Phy
  • PCIe 6.0 / CXL 3.0 PHY & Controller
    • Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
    Block Diagram -- PCIe 6.0 / CXL 3.0 PHY & Controller
  • PCIe 5.0/4.0/3.0 PHY & Controller
    • Innosilicon’s PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, storage networks, automotive, and I/O connectivity applications
    •  
    Block Diagram -- PCIe 5.0/4.0/3.0 PHY & Controller
  • PCIe GEN6 PHY IP
    • The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
    • It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
    Block Diagram -- PCIe GEN6 PHY IP
  • PCIE 6.0/5.0/4.0/3.0/2.0
    • Support PCI Expression Gen5 & Gen4 & Gen3 & Gen2 & Gen1
    • Configurable differential voltage swing
    • Embedded low jitter LC PLL with fixed bandwidth and output frequency
    • PLL Frequency Lock detection
    Block Diagram -- PCIE 6.0/5.0/4.0/3.0/2.0
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
  • PHY for PCIe 6.0 and CXL
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • Comprehensive real-time diagnostic, monitor, and test features
    • Bifurcation support for x1, x2, x4, x8, and x16 lanes
    Block Diagram -- PHY for PCIe 6.0 and CXL
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