Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
- CXL
- Silicon Proven
CXL IP cores enable high-speed serial connectivity for bandwidth-intensive systems in modern SoC and ASIC designs.
These IP cores support cache-coherent high-bandwidth connectivity for memory expansion, accelerators, and data-center-class compute fabrics, helping designers build scalable, standards-based interconnect for infrastructure, storage, multimedia, or advanced embedded applications
This catalog allows you to compare CXL IP cores from leading vendors based on throughput, latency, power efficiency, and process node compatibility.
Whether you are designing data center platforms, AI accelerators, memory expansion systems, or server SoCs, you can find the right CXL IP for your application.
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…
CXL 4.0/3.2/3/2 Verification IP
The CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or…
The SmartDV's OpenCAPI Verification IP is fully compliant with OpenCAPI TL V3.0, V3.1 and V4.0, OpenCAPI DL V1.0 and V1.5 Specifi…
GENZ Verification IP provides an smart way to verify the GENZ bi-directional bus.
CXL Verification IP provides an smart way to verify the CXL bi-directional bus.
OpenCAPI Synthesizable Transactor
The OpenCAPI Synthesizable Transactor is compliant with OpenCAPI TL V3.0, V3.1 and V4.0, OpenCAPI DL V1.0 and V1.5 Specifications…
The CXL Controller IIP core supports the CXL 1.0 and 1.1 Specification.Through its CXL compatibility, it provides a simple interf…
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network inte…
The IntelliProp IPC-GZ201A-ZM Gen-Z Switch is an IP Core that allows companies to build Gen-Z compliant components.
The IntelliProp IPC-GZ198A-ZM Gen-Z Link Layer is an IP Core that allows companies to build Gen-Z compliant devices.
The IntelliProp IPC-GZ190A-HI Gen-Z Requester is an IP Core that allows companies to build Gen-Z compliant Requester devices.
The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices.
VIP for Compute Express Link (CXL)
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CX…
The CXL Verification VIP provides an effective & efficient way to verify the components interfacing with CXL Switch interface of …
PCIe 6.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 6.0 links operating at 64 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions on…