IP Catalog > Interface IP > Interconnect IP > CXL IP

CXL IP

Welcome to the ultimate CXL IP hub! Explore our vast directory of CXL IP
All offers in CXL IP
Filter
Filter

Login required.

Sign in

Search (32)
Compare 32 CXL IP from 11 vendors (1 - 10)
  • CXL 3.1 Controller
    • Ultra-low Transmit and Receive latency
    • Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
    • Supports backwards compatibility to PCIe 6.1
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
    • Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
    • Merged Replay and Transmit buffer enables lower memory footprint
    Block Diagram -- CXL 3.1 Controller
  • CXL 2.0 Controller with AXI
    • Supports the latest CXL specification
    • AMBA AXI Layer for CXL.io
    Block Diagram -- CXL 2.0 Controller with AXI
  • CXL 2.0 Controller
    • Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
    Block Diagram -- CXL 2.0 Controller
  • Compute Express Link (CXL) 1.1/2.0/3.0 Controller
    • Implements CXL 3.0 Specification at 64 GT/s
    • Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
    • Designed for easy integration with PipeCORE™ PCIe® PHY IP
    Block Diagram -- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
  • 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
    • High speed performance
    • Low power architecture
    • Robust training
    Block Diagram -- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
  • Controller for CXL
    • The Controller IP for CXL provides the logic required to integrate a root-port (RP), end-point (EP), or dual-mode (DM) controller into any system on chip (SoC), and supports CXL 3.1, CXL 2.0 and CXL 1.1
    • Designed for lowest latency at the highest bandwidth possible and with a rich set of client interfaces available, the Cadence Controller IP for CXL allows superior flexibility for all three device types in the CXL specification
    • The Controller IP for CXL has been robustly verified with lead OEM partners in pre-silicon, and the Cadence subsystem test chips for PCIe and CXL include a CXL controller
    Block Diagram -- Controller for CXL
  • CXL Verification IP
    • Supports CXL specs revision 1.0, 1,1 and 2.0.
    • Supports Native PCIe mode and below features as defined in the PCIe specification.
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0/5.1
    • Serial, PIPE, PCS/PMA, Low pin count and SerDes interface
    Block Diagram -- CXL Verification IP
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
  • CXL Switch Verification IP
    • Available in native System Verilog (UVM/OVM/ VMM) and Verilog
    • Unique development methodology to ensure the highest levels of quality
    • Availability of Compliance & Regression Test Suites
    • 24X5 customer support
    Block Diagram -- CXL Switch Verification IP
  • CXL 3.0 Verification IP
    • Available in native System Verilog (UVM/OVM/VMM) and Verilog.
    • Unique development methodology to ensure the highest levels of quality.
    • 24X5 customer support.
    • Unique and customizable licensing models.
    Block Diagram -- CXL 3.0 Verification IP
×
Semiconductor IP