IP Catalog > Interface IP Cores > CXL IP

CXL IP

Welcome to the ultimate CXL IP hub! Explore our vast directory of CXL IP
All offers in CXL IP
Filter
Filter

Login required.

Sign in

Search (38)
Compare 38 CXL IP from 16 vendors (1 - 10)
  • Verification IP for CXL
    • Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CXL3, CXL3.1
    Block Diagram -- Verification IP for CXL
  • CXL Controller
    • Implements CXL 3.0 Specification at 64 GT/s
    • Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
    • Designed for easy integration with PipeCORE™ PCIe® PHY IP
    Block Diagram -- CXL Controller
  • 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
    • The PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s).
    • It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.
    Block Diagram -- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
  • Compute Express Link (CXL) FPGA IP
    • Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
    • First FPGA to pass CXL Consortium Compliance Program (up to 32 GT/s speed).
    Block Diagram -- Compute Express Link (CXL) FPGA IP
  • CXL Controller IP
    • The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
    • Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
    Block Diagram -- CXL Controller IP
  • CXL 2.0 Controller with AXI
    • Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    Block Diagram -- CXL 2.0 Controller with AXI
  • PCIe 6.0 / CXL 3.0 PHY & Controller
    • Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
    Block Diagram -- PCIe 6.0 / CXL 3.0 PHY & Controller
  • CXL 3 Controller IP
    • The CXL 3 Controller IP is designed to support dual-mode operation, allowing dynamic selection between host and device modes.
    • It connects to standard 64GT/s PHYs through the PIPE 6.x interface and supports high data rates across various link widths.
    Block Diagram -- CXL 3 Controller IP
  • CXL 3.1 Controller
    • Ultra-low Transmit and Receive latency
    • Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
    • Supports backwards compatibility to PCIe 6.1
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
    • Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
    • Merged Replay and Transmit buffer enables lower memory footprint
    Block Diagram -- CXL 3.1 Controller
  • CXL 2.0 Controller
    • Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
    Block Diagram -- CXL 2.0 Controller
×
Semiconductor IP