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CXL IP

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Compare 35 CXL IP from 14 vendors (1 - 10)
  • CXL 4.0/3.2/3/2 Verification IP
    • Compliant with the CXL 3.2, 2.0 & 1.1 Specification.
    • Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
    • Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
    • Support for 256B flit in 64GT/s with PCIe Gen 6 as well as 32/16/8 GT/s speeds with backward compatibility.
    Block Diagram -- CXL 4.0/3.2/3/2 Verification IP
  • CXL 3.0 Controller
    • The CXL Controller IP is micro-architected with power, performance, and area optimization for high bandwidth, minimum latency, and low power applications.
    • The CXL IP supports seamless transition from FPGA prototyping to production silicon implementation.
    • Featuring native integration with SignatureIP's Coherent and Non-coherent Network-on-Chip (NoC) IPs, this controller enables robust SoC subsystems and complete platform solutions
    Block Diagram -- CXL 3.0 Controller
  • Verification IP for CXL
    • Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CXL3, CXL3.1
    Block Diagram -- Verification IP for CXL
  • Compute Express Link (CXL) FPGA IP
    • Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
    • First FPGA to pass CXL Consortium Compliance Program (up to 32 GT/s speed).
    Block Diagram -- Compute Express Link (CXL) FPGA IP
  • CXL Controller IP
    • The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
    • Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
    Block Diagram -- CXL Controller IP
  • CXL 2.0 Controller with AXI
    • Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    Block Diagram -- CXL 2.0 Controller with AXI
  • PCIe 6.0 / CXL 3.0 PHY & Controller
    • Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
    Block Diagram -- PCIe 6.0 / CXL 3.0 PHY & Controller
  • CXL 3.1 Controller
    • Ultra-low Transmit and Receive latency
    • Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
    • Supports backwards compatibility to PCIe 6.1
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
    • Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
    • Merged Replay and Transmit buffer enables lower memory footprint
    Block Diagram -- CXL 3.1 Controller
  • CXL 2.0 Controller
    • Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
    Block Diagram -- CXL 2.0 Controller
  • CXL - Enables robust testing of CXL-based systems for performance and reliability
    • CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol. With features like protocol compliance checks, cache coherency validation, and advanced debugging tools, it ensures robust and efficient testing of high-performance computing systems.
    • From HPC and AI to automotive and edge computing, CXL Verification IP supports diverse applications. It enables seamless communication between processors, memory, and accelerators, ensuring reliable performance in data centers, ML systems, cloud infrastructures, and telecom networks.
    Block Diagram -- CXL - Enables robust testing of CXL-based systems for performance and reliability
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