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Timer/Watchdog IP for TSMC

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Compare 5 Timer/Watchdog IP for TSMC from 2 vendors (1 - 5)
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
    • The CL12832M8R2JM3KIP2400 is designed to support data rate in excess of maximum 2.4Gbps utilizing SLVS-EC / sub-LVDS / CMOS 1.8V interface specification.
    • The CL12832M8R2JM3KIP2400 can change Interface type to same PAD for changing mode.
  • MIPI D-PHY Transmitter 4-Lane (4-Data/1-Clock) 250Mbps
    • The CL12631I4T1AS1BIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12631I4T1AS1BIP2500 converts the input parallel data to the serial data and output it.
    • The CL12631I4T1AS1BIP2500 is designed to support maximum 2.5Gbps data rate utilizing mipi-DPHY_specification_v1-2.
  • MIPI D-PHY/sub-LVDS Transmitter - 8-Lane 2.5Gbps - TSMC 28nm HPC+
    • The CL12661M8T1KM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
    • The CL12661M8T1KM2JIP is designed to support data rate in excess of maximum 2.5Gbps utilizing sub-LVDS / MIPI-DPHY interface specification.
  • Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
    • The CL12842M8R2JM4TIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
    • The CL12842M8R2JM4TIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / sub-LVDS / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification.
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