Single-Port SRAM IP for TSMC
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Single-Port SRAM IP
for TSMC
from 6 vendors
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High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
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TSMC CLN5FF High Density Single Port SRAM Compiler
- The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
- ? Pins and metal layers
- – 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
- – Power mesh supported with M3 pins
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TSMC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
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Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- REACH THE HIGHEST DENSITY
- Thanks to smart periphery design
- Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
- Using Pushed Rules Foundry bitcell
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Foundry sponsored memory generator
- Configuration
- uLL TSMC Bit-cell for memory core and uLL MOS for memory periphery
- Migration of an existing architecture already available for other processes (90, 85, 55 nm)
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 320 k
- Configuration
- SVT MOS for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- Smart periphery design to reach the highest density
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Foundry sponsored - Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- FOUNDRY SPONSORED
- HIGHEST DENSITY
- -Smart periphery design
- -Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
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Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - Compiler range up to 640 k
- Reduced die cost
- Up to 10% denser than traditional memory compiler
- HVT Pushed rule foundry bitcell
- Ultra low dynamic power