Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - Compiler range up to 640 k

Overview

Single Port SRAM compiler - TSMC 90 nm LP - Memory optimized for high density and low power - Dual Voltage - Compiler range up to 640 k

Reduced die cost
Up to 10% denser than traditional memory compiler
HVT Pushed rule foundry bitcell
Ultra low dynamic power
Low power architecture even at nominal voltage: up to 50% less consuming than standard memory compilers available at 90 nm LP
Low voltage capability: 20% additional power consumption savings when operating at 1.0 V +/-10%
Byte write capability
Ultra low leakage design
Up to 25% less leaky in stand-by mode compared with standard offering at 90 nm LP
Memory designed with SVT/HVT MOS for periphery and HVT bitcell
Optional data retention mode (RR option): in which only the memory plane and the circuitry for retention remains powered. Note that this data retention mode requires 2 power supply lines and one ground
Easy integration
Mux factor can be chosen
Architecture specifically designed to limit dynamic IR Drop
Models of peak current delivered for free
Complete mismatch validation of the memory architecture taking into account local and global dispersion
Partitioned array for best low voltage performances
Sense amplifier optimized for low voltage operation
High robustness thanks to self-timing access scheme
Optional BIST for industrial fabrication test of instances

Maturity

In_Production

TSMC

In Production: 90nm LP