PCI Express Phy IP for SMIC
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PCI Express Phy IP
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PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
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USB 2.0 PHY
- Compliant with USB2.0 and USB1.1 specification
- Compliant with UTMI Specification Version 1.0
- Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
- USB Data Recovery and Clock Recovery on receiving
- SYNC and EOP generation on transmit packets and detection on receive packets
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PCIe PHY
- Support for PCIe3(8.0Gbps)，Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4.2 interface specification
- Support 16bit and 32bit parallel data bus
- Independent channel power down control
- Supported reference clock input range from 25M to 400M
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PCIe 2.1 PHY(12nm,14nm, 16nm, 28nm, 40nm, 55nm)
- Fully compliant with PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
- Compliant with PIPE4.4.1 (PCIe) specification
- Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
- Supports L1 PM Substates with CLKREQ#
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PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)
- Compliant with PC1 Express 3.0 (8.0 GT/s), 2.1 (5.OGT/s) and 1 .I (2.5GT/s) as well as the PIPE 4.0 specifications
- Supports the power saving modes L0, L0s, L1 and L2
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PCIe Gen2 PHY
- ? 5-Gbps data transmission rate
- ? PIPE3-compliant transceiver interface, configurable using soft Physical Coding Sublayer (PCS)
- layer above hard macro PHY
- ? Supports 8-bit interface at 500-MHz operation
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PCIe 2.0 PHY in SMIC (40nm, 28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options