IP Catalog > Interface IP > Interconnect IP > PCI IP > PCI Express IP > PCI Express Phy IP > PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)

PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)

Overview

M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 3.1 IP supports a complete range of PCIe 3.1 Base applications and is compliant with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support 8Gbps PCIe 3.1 traffic and is backward compatible with 5.0Gbps PCIe 2.1 and 2.5Gbps PCIe 1.1 data rates. With the support of both TX and RX equalization techniques, the PCIe 3.1 IP is designed to meet the requirements of different channel conditions.

Key Features

  • Fully compliant with PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Compliant with PIPE4.4.1 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE4.4.1 specification
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allow user-specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports robust BIST functions for mass production testing
  • Dual-mode reference clock pad: Output 100MHz clock reference clock for RC mode or receive 100MHz clock for EP mode
  • Can be configured up to multi-lane (x2, x4) design with multiple instances

Technical Specifications

Foundry, Node
6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm
SMIC
Silicon Proven: 28nm HKC+ , 40nm LL
TSMC
Pre-Silicon: 7nm
Silicon Proven: 12nm , 16nm , 22nm , 28nm HPCP , 40nm LP
UMC
Silicon Proven: 28nm HPC
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