PCIe Gen2 PHY

Overview

Key Features

• ? 5-Gbps data transmission rate
• ? PIPE3-compliant transceiver interface, configurable using soft Physical Coding Sublayer (PCS)
• layer above hard macro PHY
• ? Supports 8-bit interface at 500-MHz operation
• ? Supports 16-bit interface at 250-MHz operation
• ? Supports 32-bit interface at 125-MHz operation
• ? Integrated PHY includes transmitter, receiver, PLL, digital core, and electrostatic discharge (ESD)
• protection circuits
• ? Programmable RX equalization
• ? Supports collapsing of power supplies
• ? Supports one, two, three, or four PIPEs mapped onto 1, 2, 4, 8, or 16 lanes
• ? Integrated regulator to support either 3.3-V or 2.5-V I/O power supply
• ? Excellent performance margin and receiver sensitivity
• ? Robust PHY architecture that tolerates wide process, voltage, and temperature variations
• ? Low-jitter PLL technology with excellent supply isolation
• ? IEEE 1149.6 (AC JTAG) boundary scan
• ? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester:
• ? Supports 5-Gbps PCIe Gen 2 and 2.5-Gbps PCIe Gen 1.1 test modes
• ? Advanced, built-in diagnostics including on-chip sampling scope for easy debug
• ? Visibility and controllability of hard macro functions through programmable registers in the design
• ? Overrides on all ASIC side inputs for easy debug
• ? Access register space through simple 16-bit parallel interface
• ? Access register space through JTAG port

Deliverables

• We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Technical Specifications