The Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power.
PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 7 600 MHz Post-Divide Reference frequency FPFD 7 200 MHz VCO Frequency FVCO 8000 MHz Output Frequency FOUT 7 4000 MHz Output Duty Cycle tDO 45 55 % Area A 0.008 sq. mm Total Power IDD 4 mA Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.08 1.2 1.32 V Operational Temperature TOP -40 25 125 O C Table 1: PLL Operational Range