VME System Controller with AXI4 compliant user interface

The VMESCmodule2 is Inicore's next generation VME System Controller core designed for FPGA and ASIC integrations. The core contains VME Slave and Master functions as well as System Controller features such as bus timer, arbiter, IACK daisy-chain driver, system clock driver and provisioning for CSR.

The AXI4 compliant user-side interface simplifies system integration. The core contains internal FIFOs and address mapping logic to bridge the VME to the AXI bus and vice versa. A dedicated AXI4-lite port is provided for independent CSR access.

With this rich feature set, the core can be used as a System Controller Module, as a Master Module, or as a Slave Module. This makes the VMESCmodule2 an excellent platform to base all your future VME designs on.

This core is available in two different flavors: VMESCmodule2e contains support for 2eSST while the VMESCmodule2 does not support 2eSST. Otherwise, their features are identical.

• System Controller
  • Bus Arbiter
    • Fixed priority
    • Round robin
  • Bus Timer
    • Programmable 1-255 us timeout
  • SYSCLOCK* driver
  • SYSFAIL* driver
  • First Slot Detector
  • IACK daisy-chain driver
• Master Interface
  • Coupled transfers for single data cycles, buffered transfers for multiple data cycles (block/burst transfers)
  • Addressing modes: A16, A24, A32
  • Single cycle transfers: D08(EO), D16, D32
  • Block transfers: D32-BLT, D64-MBLT
  • Access modes: Read, write, read-modify-write
  • 8 master windows to map the AXI memory space into the VME memory space
  • Separate 4k deep read and write FIFOs to decouple AXI and VME bus transactions
• Slave Interface
  • Addressing modes: A16, A24, A32
  • Single cycle transfers: D08(EO), D16, D32
  • Block transfers: D32-BLT, D64-MBLT
  • Access modes: Read, write, read-modify-write
  • Selectable rescinding DTACK
  • Provides big-endian to little-endian conversion option
  • 8 slave windows that map the VME memory space into the AXI memory space
  • Separate 4k deep read and write FIFOs to decouple VME and AXI transactions
  • Optional AXI block data read-ahead to increase data throughput
• Interrupt Handler
  • Automatically fetches STATUS/ID vector from pending VME
  • interrupt requests
  • Supports D08(O), D16, and D32
• Interrupter
  • D08(O), D16, D32
  • Software interrupt request (ROAK)
  • User interrupt request (RORA)
  • Programmable interrupt level and type
• Bus Requester
  • RWD (release when done) and ROR (release on request) arbitration schemes
  • FAIR requester
  • Supports early withdrawal of bus request
• Local Bus Interface
  • Fully synchronous bus interface for user logic
  • User selectable wait-states
  • Optional big-endian to little-endian conversion
• Local Bus Interface
  • Standard AXI4 compliant bus interface
  • Separate AXI4-lite port for CR/CSR access
  • Big-endian to little-endian conversion
• CR/CSR
  • Contains address decoding for CR/CSR space
  • Local CSR configuration registers

• The VMESCmodule2 is a VME System Controller core designed for FPGA and ASIC integrations. The core has an AXI4 compliant user-side interface to simplify system integration.
• The core contains VME Slave and Master functions as well as System Controller features such as bus timer, arbiter, IACK daisy-chain driver, system clock driver, and provisioning for CR/CSR.
• The core contains all functionality needed for a VME system controller design.
• The core can be used together with application specific logic to mitigate technology obsolescence. The Module is an excellent starting point for future VME designs.

• VHDL RTL code
• Self-verifying system-level testbench
• Simulation and synthesis scripts
• Synthesis information
• User guide
• Hotline Support by means of phone, fax and e-mail