Versatile AES256 IP core (ECB, CBC, CFB, OFB, CTR)

Overview

The AES symmetric encryption IP cores ensure robust encryption and decryption, providing data confidentiality and integrity with the Advanced Encryption Standard algorithm.These solutions support various AES modes and offer versatile functionality for secure data communication and storage protection. The in-house designed AES encryption engines are optimised for efficiency and high performance in both FPGA and ASIC implementations.

Our AES IP cores offer various modes, ensuring performance, flexibility, and robust security.

Key Features

Optimised resource requirements
100s of Mbps
Compliant with NIST standards
CAVP validated by NIST
Support for various AES modes including GCM, CTR, XTS, ECB, CBC, CFB, and OFB
Pure RTL without hidden CPU or software components
Easy system integration
Vendor agnostic FPGA/ASIC implementation

Benefits

Several Mbps
Only ~4 kLUTs
Fully digital design
Portable to any ASIC or FPGA technology
Fully standard compliant
Easy to integrate
Several bus interfaces available
IP core designed in-house at Xiphera
Technical support by the original designers and cryptographic experts
CAVP validated

Block Diagram

Applications

Secure data communication
Data protection in storage
MACsec/IPsec/TLS
Optical transport
WPA3 support
IoT device security
Automotive security

Deliverables

Encrypted RTL or source code
Sample synthesis scripts
Comprehensive simulation test bench, scripts & guide
Optional netlist
Instantiation file
Detailed datasheet and integration guide

Technical Specifications

Foundry, Node

Any

Maturity

Hardware tested

Availability

Immediate

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