Cryptographically Secure Pseudo Random number Generator IP Core

Overview

The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90.

Basic core is small (6,500 gates) and uses an external 256-bit entropy seed to generate 16 bytes (128 bits) of random data at a time (128 bits of security strength). Versions of the core are available supporting higher security strengths (192 and 256 bits), larger amounts of generated bits (up to 219), and different internal datapath widths for size/performance tradeoff. The core includes the AES1 core.

The design is fully synchronous and available in both source and netlist form. Test bench uses vectors in plain text format.

PRNG1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Key Features

Generates cryptographically secure pseudo-random numbers
Uses the CTR_DRBG algorithm per NIST publication SP800-90
Generates 128-bit data blocks with 8, 16, 32, 64 or 128-bit wide data interface
Provides security strength of 128,192 and 256 bits
Self-contained; does not require external memory
Available as fully functional and synthesizable Verilog or VHDL, or as a netlist for popular programmable devices and ASIC libraries
Deliverables include Verilog test bench and test vectors

Block Diagram

Applications

Secure wireless communications, including 802.11i, 802.15.3, 802.15.4 (ZigBee), MBOA, 802.16e
Electronic financial transactions
Content protection, digital rights management (DRM), set-top boxes
Secure RFID
Secure Smart Cards

Deliverables

HDL Source Licenses
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- User Documentation
Netlist Licenses
- Post-synthesis EDIF
- Testbench (self-checking)
- Test vectors
- Expected results

Technical Specifications

Request Info