IP Catalog > Interface IP > Interconnect IP > USB IP > USB 3.1 IP > USB 3.1 PHY IP > USB 3.x Controller

USB 3.x Controller

Overview

Mature solution featuring xHCI Host, Device, and Dual-Role

The Controller IP for USB 3.1/3.0 offerings include xHCI Host (3.0), Device (3.0/3.1), and Dual-Role Device (3.0/3.1) controllers. USB 3.0 IP from Cadence was one of the first to receive a certification for compliance with the USB 3.0 specification from USB-IF.

Key Features

  • Full Link Power Management (U0, U1, U2, and U3) with LFPS support
  • Up to 15 IN and 15 OUT configurable endpoints
  • Power and clock gating feature support
  • Multi-channel Scatter/Gather DMA with TRB caching
  • AXI features 128-bit datapath width and 64-bit address width

Benefits

  • Complete IP Solution: PHY+ controller+ firmware solution facilitates rapid SoC development
  • Comprehensive Power and Clock Gating Feature: Enable substantial power saving applications
  • Industry-Standard Interfaces: Simplify system integration effort

Block Diagram

USB 3.x Controller Block Diagram

Technical Specifications

Maturity
Silicon Proven
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