USB 3.0 Device

Key Features

  • Complies w ith USB 3.0 standard for Super Speed(5.0 Gbps), Hi-S peed (480 M bps) and Full-Speed (12 M bps)
  • Backward compatible w ith usb2.0 and the type A connectors.
  • Technology and Process independent
  • Data Interface is Dual-simplex, 4-wire differential signaling, separate from USB2.0 signaling.
  • Supports Super speed UTMI transceiver interface with extension to the existing UTMI Interface for USB2.0
  • Configurable up to 15 additional IN or OUT Endpoints
  • Configurable FIFO sizesfrom 8 to 8,192 bytes with option of dynamic FIFO sizing
  • Compatible USB transfersupport for Control, Bulk, Interrupt and Isochronous transfers using U S B3.0
  • Transaction/Handshake Packets and the Data Packets.
  • Bus Transaction protocol is host directed and has asynchronous traffic flow . The packet traffic is explicitly routed.
  • Parametrizable endpoint features for number, transfer type, direction of transfer, maximum packet size and FIFO size
  • Built-in 32-bit synchronous AMBA AHB compatible CPU interface
  • Support for DMA access to FIFOs
  • Synchronous Dual Port RAM interface for FIFOs
  • Supports suspend and resume signaling
  • Fully synthesizable
  • Support all standard, Vendorspecific control transfer requests
  • Utility forcoreconfiguration of device descriptors and to wire endpoints.

Deliverables

  • Verilog source code and test-bench
  • scripts for simulation and synthesis

Technical Specifications

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Semiconductor IP