USB 2.0 OTG PHY IP, UMC 65nm LP process
Overview
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm LP/RVT Low-K Logic process.
Technical Specifications
Short description
USB 2.0 OTG PHY IP, UMC 65nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 65nm LP
UMC
Pre-Silicon:
65nm
LP