Universal G704-E1 Framer / Deframer Core
Overview
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier. Transmit and receive part are designed as individual blocks, both independently handle basic and multi frames. Both blocks perform functions such as overhead bit insertion / detection, CRC4 computation and check. The synchronization unit synchronizes automatically or by means of an external frame sync signal. The frame builder can be ci=onfigured which of the overhead bits are to be inserted or not.
Key Features
- Asymmetric Application (e.g. E1 - ATM, nx64 - E1, E1 - 30 BRI-Channels)
- Symmetric Application (e.g. E1-E1)
- Multi G704 on Chip (e.g E1-E2)
- Basic and Multiframe Alignment
- Alarm Bit Processing
- Customizable Error Counters
- Selectable Conditions for Loss of Sync
- CRC4 Error Checking and Monitoring
- Structural VHDL RTL Description
- Certified Core by the Standard Verification Bureau
- Gate Count ~7k (Main Building Blocks)
- Sample FPGAs Available
Benefits
- For use in
- ISDN Terminal Equipment
- Multi G704 on Chip (e.g E1-E2)
- E1-ATM Interface
- Certified Core by the Standard Verification Bureau
Block Diagram
Deliverables
- VHDL or Verilog RTL Source Code
- Functional Testbench
- Synthesys Script
- Data Sheet
- User Guide
- Hotline Support by means of phone, fax and e-mail
Technical Specifications
Foundry, Node
Technology independent
Maturity
Proven in ASIC and FPGA Technologies
Availability
now