UMC 65nm SP/RVT Logic Process MPCA cell library
Overview
UMC 65nm SP/RVT Logic Process MPCA cell library
Technical Specifications
Foundry, Node
UMC 65nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
65nm
LL
,
65nm
LP
,
65nm
SP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- SMIC 0.13um Low Leakage UHD RVT_x005F_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.
- SMIC 0.13um Low Leakage high density RVT_x005F_x000D_ Logic standard cell library.
- SMIC 0.13um Generic UHD RVT_x005F_x000D_ Logic standard cell library.
- IBM 65nm LPE 3.3V Standard Cell