UMC 55nm LP process with PG Dual port SRAM compiler
Overview
UMC 55nm LP process with PG Dual port SRAM compiler
Technical Specifications
Short description
UMC 55nm LP process with PG Dual port SRAM compiler
Vendor
Vendor Name
Foundry, Node
UMC 55nm Logic/Mixed_Mode LP
UMC
Pre-Silicon:
55nm
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra low leakage and high density - Dual Voltage - compiler range up to 640 k