UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
Overview
UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
Technical Specifications
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- ONFI IO v4.1, 1.2T/s, UMC 22ULL, 1.8V, N/S orientation, H&V cell
- ONFI IO v4.0, 800MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- ONFI IO v3.2, 533MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options