UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
Overview
UMC 40nm LP/RVT Logic Process 1.8V ONFI 3.2 BOAC I/O cell library
Technical Specifications
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- ONFI IO v4.1, 1.2T/s, UMC 22ULL, 1.8V, N/S orientation, H&V cell
- ONFI IO v4.0, 800MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- ONFI IO v3.2, 533MT/s, UMC 28HPC+, 1.8V, N/S orientation, H&V cell
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- CSMC 0.18um Standard Cell Library, 1.8v operating voltage