UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
Overview
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
Technical Specifications
Short description
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
Vendor
Vendor Name
Foundry, Node
UMC 40nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
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- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
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