UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
Overview
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
Technical Specifications
Short description
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
Vendor
Vendor Name
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
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- UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
- MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF
- MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF