UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
Overview
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
Technical Specifications
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- HHGrace 0.11um LP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- TSMC CLN5FF Ternary Content Addressable Memory Compiler with Column Redundancy
- TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy