UMC 28nm HPC process Dual Port SRAM compiler
Overview
UMC 28nm HPC process Dual Port SRAM compiler
Technical Specifications
Foundry, Node
UMC 28nm Logic/Mixed_Mode HPC
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
Related IPs
- CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k