UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming
Overview
UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming
Technical Specifications
Foundry, Node
UMC 0.11um
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
110nm
Related IPs
- UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming
- UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4
- Single Port SRAM Compiler IP, UMC 65nm SP process
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- SMIC 0.13um Low Leakage UHD RVT_x005F_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.
- SMIC 0.13um Low Leakage high density RVT_x005F_x000D_ Logic standard cell library.