Ultra-Low Power Fractional-N digital PLL for IoT Applications in 40nm CMOS
Overview
IMEC’s divider-less All-Digital Phase Locked Loop (ADPLL) combines world’s lowest power consumption with state-of-the-art performance and small silicon area. The ADPLL supports industrial requirements for popular 2.4GHz and SubGHz IoT radio standards, such as Bluetooth Low Energy (Bluetooth Smart), IEEE 802.15.4 (ZigBee, Thread) and others.
Key Features
- Support ULP 2.4GHz/SubGHz IoT , e.g.,
- 2.4GHz :
- Bluetooth 4.0 (BLE), 4.2 and 5.0
- IEEE802.15.4 (ZigBee, ISA100.11a,WirelessHART, Thread, 6LoWPAN)
- SubGHz:
- IEEE802.15.4g (Wi-SUN), IEEE802.11ah (HaLow)
- Ultra-low power (ULP) consumption: < 0.7mW
- Best-in-class performance
- Jitter < 2ps
- Spur < -55dBc (in-band)
- Spur< -70dBc (>2MHz)
- Settling time< 15ms
- Features
- Extensive built-in self calibrations
- Advanced power-efficient spur mitigation
- Robust against freq. pulling/pushing with digital unwrap
- Designed in TSMC 4nm LP for 1V nominal supply
- Communications
- Data processing
- Consumer Electronics
- Automotive
- Industrial and medical
- Whitebox IP license with technology transfer training and support
Applications
Deliverables
Technical Specifications
Foundry, Node
TSMC, 40nm
Maturity
Silicon proven on prototypes
TSMC
Silicon Proven:
40nm
LP
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