This ultra-low-power 12-bit ADC IP is a general purpose Analog to Digital Converter (ADC) for low-power applications based on successive approximation register architecture with a core sampling frequency ranging from 100 KS/s up to 1 MS/s. The ultra-low power is achieved by employing an advanced comparator based on the bulk biasing principle. Therefore, only dynamic current is consumed and the power consumption is fully proportional to the sampling rate.
This ADC IP features an outstanding dynamic performance that includes 66 dB SNR, -72 dB THD, and 10.5-bit ENOBs. The obtained figure of merit is only 16 fJ/Sampling rate/Conv-step for a sampling frequency of 1 MS/s excluding references.
Ultra-low-power 12-bit SAR ADC with lowest voltage
Overview
Key Features
- Standard process (no analog option)
- 0.5 V Digital & 0.9 V analog supplies
- 12-bit SAR-based
- Differential input signal range: 1.8 Vdiffpp
- Sampling rate from 100 KS/s up to 1 MS/s
- Power consumption scaling with frequency
- Internal biasing system
- Static performance: DNL < ±0.9 LSB; INL < ±1.5 LSB
- Dynamic performance @ 1 MS/s: 66dB SNR at fin=100KHz; -72dB THD at fin=100 KHz
- Ultra-low-power dissipation: only 25 uW excluding references
- Compact die area: only 0.15 mm2 excluding references
- Operating temperature range: - 40°C- 85°C
- Power down current: < 10 nA typ
Block Diagram
Applications
- Low-power data acquisition
- Sensor applications
- Portable medical equipment
- Radio baseband processing
- Hard drives
Technical Specifications
Foundry, Node
GF 22FDX, UMC 55nm, USJC 55nm
Maturity
Silicon-proven