IP Catalog > Memory Controller/PHY IP > UFS IP > UFS 3.0 Host

UFS 3.0 Host

Overview

The Universal Flash Storage 3.0 (UFS 3.0) is a simple but high-performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.

Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage and bootable storage memory with an option for an external card.

The IP incorporates the latest UFS Host Controller Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 IP is available in GDSII format for a variety of process technologies and MIPI UniProSM version 1.8 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation.

Key Features

  • UFS 3.0 Host and Device configurations available
  • Complete UFS 3.0 hardware implementation
  • Interop-proven UniPro 1.8 link layer
  • MIPI M-PHY 4.0 Interface
  • High-speed mode Gear 1, Gear 2, Gear 3, and Gear 4.
  • Supports 2 lanes for 23.3 Gbps max bandwidth
  • Task management operations
  • Supports multiple partitions (LUNs) (to dummy memory) with partition management
  • Definable write-protect group size
  • Boot mode operation
  • Device enumeration and discovery
  • Background operations
  • Secure Erase and Trim operations enhance security
  • Supports Write-protect option

Benefits

  • Seamless integration from PHY to Software
  • Assured compliance across all components
  • Single point of support
  •  Easiest acquisition process (one licensing source)
  •  Lowest overall cost including the cost of integration
  •  Lowest risk for fast time to market

Block Diagram

UFS 3.0 Host Block Diagram

Deliverables

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

Technical Specifications

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