UART Serial Interface Controller
Overview
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC technologies.
Key Features
- UART-compatible interface
- AMBA APB3 bus
- Full duplex
- Custom baud rate generation
- 8x, 16x oversampling
- 5, 6, 7, 8, 9 bits data
- 1, 2 stop bits
- LSB or MSB mode
- Configurable parity
- Hardware flow control
- RS485 mode
- Maskable interrupts
- Dedicated upstream and downstream DMA interface
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Silicon and FPGA proven
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Block Diagram
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Technical Specifications
Related IPs
- UART with FIFOs, IrDA, and Synchronous CPU Interface Core
- Multi-Rate Serial Digital Interface (SDI) PHY Layer
- Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- DO-254 UART Serial Interface Controller 1.00a
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support