IP Catalog > Memory & Libraries IP > Embedded Memories IP > CAM IP > TSMC CLN16FFC Ternary Content Addressable Memory

TSMC CLN16FFC Ternary Content Addressable Memory

Overview

IGMTLSLV02A is a synchronous LVT periphery high-density ternary content addressable memory (TCAM). It is developed with TSMC 16 nm 0.8 V/1.8 V CMOS LOGIC FinFET Compact Process. Different combinations of words, bits can be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMTLSV02A compiler is capable of providing suitable synchronous TCAM layout instances within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation.

Key Features

  • Ternary Content Addressable Memory (TCAM) operates within a voltage range from 0.72 V to 0.88 V and a junction temperature range from -40 oC to 125 oC. The available supported macro size is configured from 128 bits to 80K bits.
  • Pins and metal layers
  • 5 metal layers used and top metal is Mxe_v
  • Power mesh with M5 pins support
  • General feature
  • TSMC 16T 0.345 um2 NOR TCAM bit cell
  • Full-customized design to optimize for performance, power and area
  • Two arrays, Data and Mask arrays, used to encode 0, 1 or X
  • Memory control pins for read/write and compare
  • Global mask input for bit-write and masked-key search capability
  • Dynamic compare power saving by appropriately configuring bank enable pins
  • Valid bit per entry
  • MATCHLINE outputs
  • Supports BIST code
  • Frequently used EDA model support
  • CPODE layer (206;32) used in layout design

Technical Specifications

Foundry, Node
TSMC 16nm CLN16FFC
Maturity
Silicon proven
TSMC
Silicon Proven: 16nm
Request Info

Related IPs

×
Semiconductor IP