IGMTLSV04A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM). It is developed with TSMC 12nm 0.8V/1.8V CMOS LOGIC FinFET Compact Process. Different combinations of words and bits could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMTLSV04A compiler is capable of providing suitable synchronous TCAM instances models within minutes. It is capable of automatically generating data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold times and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.
TSMC CLN12FFC Ternary Content Addressable Memory Compiler
Overview
Key Features
- Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.72V to 0.88V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 128bits to 80K bits.
- Pins and metal layers
- 1P5M (2Xa1Xd_h_1Xe_v): 5 metal layers used and top metal is Mxe_v
- Power mesh supported with M5 pins
- General features
- TSMC 16T 0.345um2 NOR TCAM bit cell
- Full-customized design to optimize for performance, power and area
- Two arrays, Data and Mask arrays, used to encode 0, 1 or X
- Memory control pins for read/write and compare
- Global mask input for bit-write and masked-key search capability
- Dynamic compare power saving by appropriately configuring bank enable pins
- Valid bit per entry
- MATCHLINE outputs
- Supports BIST/ECC code
- Frequently used EDA model support
- CPODE layer (206;32) used in layout design
- BIST compiler features
- BIST RTL compiler enabling TCAM complete read, write, search function tests with various data background
- Support multiple instances wrapper, testing in serial
- Support fault injection option in simulation model
- Support test bench for basic verification
- Error flag to identify the test result of TCAM R/W, Compare function, and control signals
- ECC system features
- Pure soft macro RTL compiler to support SEC/DED for Read/Write operation and SCRUB mode
- Support auto scrub mode with programmable timing interval
- External scrub could be requested by system with interrupt control
- External standard SRAM could be used for ECC bits
- Support RTL wrapper for system integration and test bench for verification
Technical Specifications
Foundry, Node
TSMC 12nm CLN12FFC
Maturity
Pre-silicon
TSMC
Pre-Silicon:
12nm
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