Triple Video DAC 10-Bits, 240Mhz

Overview

This IP is composed of a triple channel 10-bits 240 MS/s DAC, designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V.
Each independent DAC uses a segmented current steering architecture, combined with improved twodimensional centroid switching scheme, to achieve simultaneously high update rates, at least 10-bit of intrinsic static accuracy, and a very good dynamic
characteristics.
The differential output supports single-ended applications and is designed to be loaded by double 75Ω line termination, (37.5Ω).
An external resistor, 1k8Ω typical is used to set the full scale current of the DAC.

Key Features

10-Bits Resolution
240MS/s Update Rate
3.3V ±10% supply voltage, -40/+125°C temperature.
1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
Individual DAC channel Power down.
Do not require extra external bias circuit.
Cell area: [contact us]
Built in I/Os with ESD protection on 75um pad pitch.
Antenna diodes on each digital input.
Silicon proven.

Benefits

low cost
easy integration

Deliverables

Design Kit includes:

LEF view and abstract gdsII
Verilog HDL behavioral model
Liberty (.lib) timing constraints for typical, worse and best corner case
Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Tapeout kit includes the design kit plus plysical view:

gdsII
LVS netlist and report
DRC/ERC/ESD/ANT report

Technical Specifications

Maturity

silicon proven

Availability

now

SMIC

Pre-Silicon: 180nm G

TSMC

Pre-Silicon: 180nm G
Silicon Proven: 180nm G

UMC

Pre-Silicon: 180nm

Request Info