Tessent RISC-V trace and debug

Overview

The Tessent Enhanced Trace Encoder is the market-leading trace solution for RISC-V. It is a fully-featured solution that provides a mechanism to monitor the program execution of a CPU in real time. It encodes program execution (instruction trace) and optionally, the data from load and store instructions (data trace), outputting trace in a highly compressed format.

The Tessent Enhanced Trace Encoder is designed to meet the official RISC-V Efficient Trace (E-trace) specification produced by the Debug and Trace Working Group. This group was led by representatives from Siemens who donated the trace algorithm to the RISC-V International community.

In addition to providing all the mandatory and optional features defined in the E-trace specification, the Tessent Enhanced Trace Encoder is cycle accurate, which means the developer gets insights into each and every instruction.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

Key Features

Instruction trace
Efficient packet format
Fast profiling
Multiple retirement
Data trace
Filters and comparators
Timestamps
Implicit return mode
Branch prediction
Jump target cache mode
Implicit exception mode
Sequentially inferable jump mode
Cycle accurate trace

Benefits

The most capable RISC-V trace solution on the market
Part of the Tessent Embedded Analytics whole system solution

Block Diagram

Deliverables

Parameterized soft core (Verilog RTL)
Verification trace decoder
Available UVM verification IP

Technical Specifications

Maturity

In silicon

Availability

Now

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