Stream Buffer Controller

Overview

The Stream Buffer Controller IP Core implements a versatile Stream to Memory Mapped DMA bridge with 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GB memory size. It provides AMBA® AXI4-Stream interfaces for each write and read data stream. A common memory-mapped master interface (AXI or Avalon) is provided to access the external memory device over an interconnect.

Key Features

The IP Core supports four different operation modes for each channel:

FIFO mode: writing and reading to the memory is done over the AXI4-Stream interfaces
Write mode: Writing to the memory is done over the AXI4-Stream, Reading from the memory is done by a CPU.
Read mode: Writing to the memory is done by a CPU, reading from the memory is done over the AXI4-Stream interface.
ROM mode: Reading from the memory is done over the AXI4-Stream interface. The memory must be initially written by a CPU

Supports up to 16 write and read streams (depending on product options)
Configurable status flags for write and read path
Vendor-independent implementation
Available with Avalon or AMBA-AXI interface
Data width conversion to/from any byte-multiple width

Benefits

Supports data width conversion for the write and read data streams
The use of different operation modes provides the implementation of versatile applications with a single IP core.
Easy integration thanks to the unified bus interface and the clearly laid out register bank
A stand-alone solution without the need of a CPU can be easily realized by a stream configuration controller that is provided in VHDL

Block Diagram

Applications

Data acquisition
Image processing
Test and measurement
Embedded processing

Deliverables

Stream Buffer Controller IP Core

VHDL source files (plain or encrypted, depending on product options)
Precompiled ModelSim® simulation libraries
User manual (PDF download)

Stream Buffer Controller API

C object and header files
Application software example
User manual (PDF download)

Stream Buffer Controller IP core reference design

Reference design top-level VHDL file (plain VHDL)
UCF / XDC / SDC constraint files (depending on product options)
Xilinx Vivado™ / Altera® Quartus® II project files (depending on product options)
Top-level simulation test bench file (plain VHDL)
Top-level simulation ModelSim project file
Documentation

Technical Specifications

Maturity

In beta phase

Request Info