DMA Controller
Key Features
- Multiple independent DMA channels
- Designed with synthesizable HDL for ASIC and PLD implementations in variou system environments
- Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
- Supports both hardware initiated transfer and software initiated transfers.
- Programmable burst and single data transfer.
- Internal arbitration logic for multiple DMA channels.
- Interrupt generation on transfer completion.
- Optional DMA chaining for multiple DMA sessions.
Technical Specifications
Foundry, Node
ASIC and FPGA
Availability
Now
Related IPs
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- Compactflash/PCMCIA Slave Controller
- Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
- CAN 2.0 Controller with DMA