SPI Serial Peripheral Interface Master/Slave
Overview
The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemented on FPGA and ASIC technologies.
Key Features
- SPI-compatible interface
- AMBA AXI4-Lite bus
- Master or slave mode
- Full duplex
- Programmable clock rate up to PCLK/2
- Slave speed up to PCLK/8
- Up to 8 slave select lines
- Slave MISO output enable generation for multiple slaves
- Configurable clock polarity and phase
- LSB or MSB mode
- 8, 16, 24, 32 bits data transfer mode
- Maskable interrupts
- Dedicated upstream and downstream DMA interface
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Silicon and FPGA proven
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Block Diagram
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Technical Specifications
Availability
Now
UMC
Silicon Proven:
130nm
Related IPs
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
- SPI Master/Slave- Serial Peripheral Interface
- SPI Serial Peripheral Interface Master/Slave
- Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support
- Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s