Version 1.8 Now Supports Spartan™-3/3E/3A
The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. The PCIe PIPE Endpoint LogiCORE combined with a discrete PCIe PHY offers a complete PCIe Endpoint solution fully compliant to the PCI Express Base Specification v1.1.
Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Overview
Key Features
- Compliant to PCI Express Base Specification v1.1
- Discrete PHY Interface
- PXPIPE - Interface to NXP discrete PHY
- 8-bit 250MHz interface
- 100 MHz reference clock
- Support for spread spectrum clock to reduce EMI
- Single PCIe 2.5 Gbps lane
Technical Specifications
Related IPs
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 1.1 Controller with PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Virtex-5 Endpoint Block Plus Wrapper for PCI Express (PCIe)
- Endpoint for Gen1 PCI Express