SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application

Key Features

  • DDR3/DDR2/LPDDR2 COMBO interface for DRAM application;
  • SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
  • Cell Size (Width * height) 40um * 270um with DUP stagger bonding pads;
  • Work IO voltage: 1.2V/1.5V/1.8V;
  • Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066;
  • Suitable for 7, 8, 9 and 10 layers application ;

Technical Specifications

Foundry, Node
SMIC 65nm LL
Maturity
Silicon Proven
SMIC
Silicon Proven: 65nm LL
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Semiconductor IP