SMIC 0.18um IO Library
Overview
SMIC 0.18um process 1.8v/3.3v Generic IO library
Key Features
- SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V Process.
- 3.3V I/O, 1.8V Core, 5V Tolerant.
- Both Inline and Stagger Compatible IO Pads.
- Configurable Input-Output and Skew Rate Control.
- Robust ESD (>2000V) and Latch-up Immunity (+/-200 mA).
Technical Specifications
Foundry, Node
SMIC 0.18um
Maturity
Silicon Proven
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL
Related IPs
- Silterra 0.18um ULL Process 7track Std Cell Library
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- I/O LIbrary
- I3C I/O Library
- ECO Library IPs at SMIC 40LL Process
- ECO Library IPs at SMIC 40ULP Process