Single Port SRAM Compiler IP, UMC 40nm LP process
Overview
UMC 40nm LP/LVT Single Port SRAM compiler with Power Gating & row redundancy.
Technical Specifications
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
Related IPs
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k