HyperRam in production since 2018 for many production designs.
The Cadence® Memory Model Verification IP (VIP) for HyperRam provides verification of the HyperRam controller using the HyperBus as well as xSPI Interface protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperRam is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: Features of Cypress (Infineon) and Winbond. The Cypress (Infineon) HyperRam device supports both interfaces: HyperBus as well as Octal Interface as HyperRam1.0 and HyperRam2.0 respectively.
