Silterra 0.11um Ultra Low Leakage 6track Std Cell Library
Overview
Silterra 0.11um Ultra Low Leakage 6track Std Cell Library
Key Features
- Silterra 0.11um Ultra Low Leakage Process
- Wide Variety of Cell Functions and Drive Strengths
- Process-Specific Optimization for Ultra High-Density and Low-Power
- Engineered for Synthesizability and Routability
- Scan Flip-flops for Design for Testability Support
- Clock Gating for power optimization
Technical Specifications
Foundry, Node
Silterra, 0.11um
Maturity
Silicon Proven
Related IPs
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- A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
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