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SERDES PHY IP

Overview

The Multi-protocol SerDes (MPS) PHY is a comprehensive PAM-4 solution that provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The SerDes IP has supported data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-Kr, CEI, XAUI, USXGMII, QSGMII, and SGMI. The SerDes PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline, and wireless 5G infrastructure applications. With the help of both the TX and RX equalization techniques, the SerDes IP can meet the needs of various channel conditions. It is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today’s most challenging system environments and applications. This makes the PHY ideal for many long-reach, copper and backplane system environments.

Key Features

  • Multi-protocol PHYs supporting data rate in the range of 1.25G to 10.3125Gbps
  • Support >20dB channel loss
  • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration.
  • Support RX loss-of-signal detect
  • Support x1, X2, and X4 lanes
  • LC-PLLs provide a wide range of operating frequencies
  • Wide range programmable multipliers for reference clock multiplication
  • Accessible register controls allows user specific optimization of critical parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Built-in Self Test (BIST) support
  • At-speed functional test capability with low-speed reference clocks
  • Internal serial loopback with optional phase advancing
  • Parallel loopback supported within the PMA
  • Support both FOM for Link-EQ Training
  • Support robust BIST functions for mass production tests
  • Optional MDIO interface can be provided as required for Ethernet standard PHYs
  • PHYs are spec compliant across a wide operating junction temperature range (-20 °C to 125 °C). PLLs, bias circuits, and data path are functional between -40 °C to -20 °C
  • Support Wire-Bond and Flip-Chip packages
  • AC-coupled RX front end with on-chip capacitors
  • Available in 28nm and 16nm/12nm process nodes

Benefits

  • Duplex lane configurations of x1, x2, x4, and x8
  • Support for AC-coupled interfaces
  • A wide range of PLL multiplication options supporting low reference clock frequencies
  • Flexible ASIC clocking
  • 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  • Deterministic latency with in +-1UI variation for Tx lane
  • Second-order CDR meeting SSC and RX sinusoidal jitter requirements
  • Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
  • Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
  • Built-in PRBS pattern generation and checking for standalone loopback testing
  • Operation across a wide temperature range (-40 C to +125 )

Applications

  • Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Deliverables

  • Datasheet
  • SoC Integration guide
  • PMA Hard Macro and Design Kit
  • Verilog models
  • LEF abstracts (.lef)
  • Timing models (.lib)
  • CDL netlists (.cdl)
  • ATPG scan and IEEE 1149.6 AC boundary scan
  • IBIS-AMI models
  • GDSII layout
  • DRC & LVS reports
  • Optional design integration and bring-up support services

Technical Specifications

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